The present invention relates to integrated circuits, and, more particularly to a current or voltage generator integrated onto a silicon wafer.
A current or voltage generator 10 of the above-mentioned type is represented in FIG. 1. The circuit 10 comprises two branches B1 and B2. The branch B1 comprises a PMOS transistor TP1 the drain of which is connected to the drain of an NMOS transistor TN1, the source of the transistor TN1 being connected to ground through a resistance R1. The branch B2 comprises a PMOS transistor TP2, the drain of which is connected to the drain of an NMOS transistor TN2, and the source of the transistor TN2 is connected to ground. The transistor TN1 has a gate width to length ratio, or W/L ratio, equal to n times that of the transistor TN2, and is generally produced by n NMOS transistors TN1-1, TN1-2, . . . TN1-n in parallel, that are identical to the transistor TN2. The transistors TP1, TP2 receive a voltage Vcc on sources S and are arranged as current mirrors, with the gate G of the transistor TP2 being connected to the gate of the transistor TP1 which is itself connected to the drain D of the transistor TP1.
So that the circuit 10 self-biases at a determined operating point, the gate of the transistor TN1 is connected to the gate of the transistor TN2 which is itself connected to the drain of the transistor TN2. After application of the voltage Vcc, the generator 10 sets to an operating point where the branches B1, B2 are passed through by the same current I, taken to be constant.
The generator 10 delivers a reference voltage Vref that is, for example, sampled at the gate of the transistor TN1. To obtain a constant source of current, the voltage Vref is applied to the gate of an NMOS transistor TN0 arranged in an external branch Be. The voltage Vref imposes a current Ie(Vref) in the branch Be. This current is equal to the current I if the transistor TN0 is identical to the transistor TN1, otherwise it is proportional to the current I. The transistor TN0 is therefore the equivalent of a current generator inserted into the branch Be. Other current generators can be created in this way by applying the voltage Vref to other transistors.
The current or voltage generator that has just been described provides the advantage of being very simple and small in size in terms of silicon surface. However, it is inconvenient in that it is sensitive to temperature variations, and to variations in the supply voltage Vcc. For a better understanding, FIG. 2 represents current Ie(Vref) curves according to the temperature T and to the voltage Vcc. It can be seen that the current Ie(Vref) varies with the temperature, for a given supply voltage Vcc. Furthermore, for a given temperature T, it can also be seen that the current increases when the voltage Vcc increases.
The purpose of the present invention is to overcome this shortcoming in a simple manner, without using complex stabilization circuits.
More particularly, the purpose of the present invention is to provide a current or voltage generator of the afore-mentioned type that has good temperature stability.
The purpose of the present invention is also to provide a current or voltage generator of the afore-mentioned type that remains stable when its supply voltage varies.
For these purposes, the present invention provides a generator comprising two elements that can have identical temperature stability points. More particularly, the present invention provides a current or voltage generator integrated onto a silicon wafer, comprising a first element comprising a first NMOS transistor having its source connected to ground through an electrical resistance, and a second element comprising a second NMOS transistor having its source connected to ground. The generator may also include a bias circuit for the first and second elements. The second element may comprise a voltage divider, the gate of the second NMOS transistor may be connected to a dividing node of the voltage divider, and the anode of the voltage divider may be connected to the gate of the first NMOS transistor.
According to one embodiment, the voltage divider comprises at least two resistances, and the gate of the second NMOS transistor is connected to the midpoint of the two resistances.
According to one embodiment, the bias circuit applies an identical drain-source current to the first and second elements, such that the first and second elements have a common operating point in current and in voltage.
According to one embodiment, the first and second elements are arranged to have the same temperature stability point, i.e. current/voltage curves according to the temperature of each element that meet at the same point.
According to one embodiment, the bias circuit is arranged so that the common operating point of the first and second elements corresponds to the temperature stability point of the first and second elements.
According to one embodiment, the bias circuit comprises a first branch connected to the drain of the first NMOS transistor, a second branch connected to the drain of the second NMOS transistor, and a third branch connected to the anode of the divider. The first branch and the second branch may be arranged as current mirrors.
According to one embodiment, the first branch and the second branch respectively may comprise a first PMOS transistor and a second PMOS transistor.
According to one embodiment, the first branch may comprise a third NMOS transistor arranged between the first PMOS transistor and the first NMOS transistor, the second branch may comprise a fourth NMOS transistor arranged between the second PMOS transistor and the second NMOS transistor, and the third branch may comprise a fifth NMOS transistor having its gate connected to those of the third and fourth NMOS transistors.
According to one embodiment, the bias circuit comprises a fourth branch comprising a third PMOS transistor in series with a sixth NMOS transistor. The third PMOS transistor and the sixth NMOS transistor may be arranged to maintain a voltage on the drain of the first PMOS transistor that is substantially identical to the drain voltage of the second PMOS transistor.
According to one embodiment, the gate of the third PMOS transistor may be connected to the drain of the first PMOS transistor, and the gate of the sixth NMOS transistor may be connected to the gate of the second NMOS transistor.
According to one embodiment, the second PMOS transistor may have its drain connected to its gate and its gate connected to the gate of the first PMOS transistor.
According to one embodiment, the first NMOS transistor may comprise a plurality of NMOS transistors in parallel.
According to one embodiment, the generator may comprise an output delivering a reference voltage equal to the gate voltage of the first NMOS transistor.
According to one embodiment, the generator may comprise an output delivering a reference voltage equal to the gate voltage of the second NMOS transistor.
According to one embodiment, at least one gate of the first or second NMOS transistor may be connected to the gate of a transistor arranged in an external branch to form a source of current.